AFTER POWER ON:

CTRL.ASDE = 1
CTRL.SLU = 1

82541xx or 82547GI/EI - set LED with LEDCTRL

CTRL.LRST = 0
CTRL.PHY_RST = 0
CTRL.ILOS = 0   (not on 82541xx and 82547GI/EI)

FCAH,FCAL,FCT,FCTTV = 0   (if no flow control is desired)
CTRL.VME = 0 (if no VLAN support is desired)

82541xx and 82547GI/EI - clear all statistical counters


Receive:

RAL/RAH - fill with MAC address
zero the MTA table

Program the Interrupt Mask Set/Read (IMS) register to enable any interrupt the software driver
wants to be notified of when the event occurs. Suggested bits include RXT, RXO, RXDMT,
RXSEQ, and LSC. There is no immediate reason to enable the transmit interrupts.

RXT0 - sets mask for Receiver Timer Interrupt
RX0 - Sets mask for on Receiver FIFO Overrun
RXDMT - Sets mask for Receive Descriptor Minimum Threshold hit
RXSEQ - Sets mask for Receive Sequence Error
LSC - sets mask for link status change


Transmit:

set descriptor buffer address in TBAL+TBAH
set TDLEN
set TDH/TDT to zero's
init TCTL.EN = 1, TCTL.PSP = 1, TCTL.CT = 10b, 
TCTL.COLD = 0x40 (full duplex, 10/100 halfduplex), 0x200 (gigabit half duplex)
set TIPG: